EP32 RISC Processor IP: Description and Implementation into FPGA

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A 32 Bit RISC Processor in VHDL. VHDL Code Package ordered separately includes Simulator.
It seems to be impossible, but you can design your own 32 processor system. Here with the help of the free to download Lattice Diamond Software just needed to program the FPGA.
The image includes the synthesized VHDL and the eForth and is programmed into the FPGA, start your favorite Terminal program and reset the Brevia board - writing code can start. More details to be found at https://wiki.forth-ev.de/doku.php/pro...
No additional hardware needed to get started, communication and Power Supply via the same USB cable.

From the book:
The eP32 microprocessor is a Minimal Instruction Set Computer , vis-à-vis Complicated Instruction Set Computer and Reduced Instruction Set Computer . MISC was originally developed by Mr. Chuck Moore, and implemented in his MuP21 chip. It happened that Chuck also invented the FORTH programming language. For many years, Chuck sought to put FORTH into silicon, because he thought FORTH was not only a programming language, but also an excellent computer architecture.

In the early 1990s, a group of engineers from the MOSIS multiple design chip service program came to Silicon Valley and started Orbit Semiconductor Corp, offering foundry services to the general public. Their service was based on a 1.2 micron CMOS processes on 5 inch wafer, with two metal layers. The smallest design they accepted was on a 2.4mmx2.4mm silicon die. Chuck figured that he could design a 20 bit CPU in that small area. It was named MuP21, because it was a multiprocessor chip, with a 20 bit CPU core, a DRAM memory coprocessor, and a video coprocessor, and all registers and stacks in the CPU core were 21 bits wide, with an extra bit to preserve the carry bit.

Because of very limited silicon area, the MuP21 had a very small set of instructions, but they were sufficient to support a complete FORTH operating system and very demanding applications with real time NTSC video output. The chip was produced and verified, but productions in plastic packages were not successful because of poor yield.

When FPGA chips became available, I tried to implement FORTH chips based on MuP21 instruction set. The first experiments were on an XS40 Kit from Xess Corp. It had a Xilinx VC4005XL FPGA on board with a 32 kB SRAM chip and an 8051 microcontroller. The purpose of this kit was to demonstrate how easy it was to use an FPGA to replace all glue logic between RAM and 8051, and to build a complete working microprocessor system. I managed to squeeze a 16-bit microprocessor, P16, into the VC4000XL chip and eliminated the 8051.

Over the years, Xilinx added more logic gates and RAM blocks to their FPGAs, and I was able to put a 32-bit microprocessor, P32, into a VCX1000E chip to host a FORTH system. This design was also ported to FPGA chips from Altera and Actel. P32 gradually evolved into eP32 with an eForth operating system. eForth is a very simple FORTH operating system designed specifically for embedded systems. However, FPGA chips were expensive, development boards were expensive, and development software tools were especially expensive. I talked about eP32 implementations, but very few people in the audience had these development tools to explore FPGA designs.

It was therefore very exciting to learn about the LatticeXP2 Brevia Development Kit, which was on sale for $49. Development software was free to download. The Kit has a LatticeXP2-5E-6TN144C FPGA chip, which has enough logic cells to implement eP32, and enough RAM memory to host the eForth system. Its RAM memory is mirrored in flash memory on chip, and you do not need external memory chips for programs and data.